With the recent advancements in very-large-scale integration (VLSI) technology, the complexity of various integrated circuits (ICs) has increased. Today, ICs include numerous functional modules like processor, memory, timers, counters, voltage regulators, etc. The various functional modules may be integrated on a single IC to enable the IC to operate as a standalone system, referred to as a system-on-chip (SOC).
Memory, in particular, forms the largest part of an SOC. A typical memory includes a number of transistors. In the recent past, the size of transistors used in memories has decreased. The transistors are therefore densely packed in the SOC to increase its functionality. However, due to such a dense integration, the transistors and, in turn, the memories become susceptible to functional stress, environmental stress, and fabrication faults.
In memories, for example, read-only memories (ROMs), various types of faults, such as stuck-at faults, word line coupling faults, bit line coupling faults, and delay decoder faults, occur. Occurrence of any such fault may cause failure of a functionality of the SOC or of the SOC itself. Thus, the testing and diagnosis of memory failures becomes important.
Testing and diagnosis of a faulty memory help in identifying the exact location of defect(s) in the memory. In the memories, testing and diagnosis can be done either externally or internally. External testing offers limited control for embedded memories. For testing the faults internally, methods such as Built-in Self Test (BIST) are implemented as test circuits fabricated along with the memory.
The test circuit generates test patterns and reads the contents of the memory in order to test and diagnose the faults present in the memory. Upon determining a fault, the BIST circuit outputs contents of the memory to a tester for further diagnosis and correction. Such testers have a limited memory and data transfer speed, thus increasing time taken for debugging the memory contents.